Project Title

1 Design of a high security Sha-3 keccak algorithm
2 Error correcting unordered codes for asynchronous communication
3 Low power multipliers for digital FIR filters
4 Design of a high speed RC6 algorithm
5 A very high speed(100gbps) AES implementation for next generation internet security
6 Efficient hardware architecture for Sha-2 Hashing scheme
7 Design of an efficient architecture for high speed serial-serial multiplier with on the fly accumulation by asynchronous counters
8 Modified DES encryption algorithm with improved BER performance in wireless communication
9 Cordic based implementations for sine and cosine calculations using verilog
10 Efficient implementations of hyperbolic functions based on cordic algorithm
11 A very efficient hardware for AES-GCM implementation
12 Optimized design of UART IP soft core based on DMA mode with auto tuning
13 A very high speed design of Context adaptive variable Length Decoder for high definition for HDTV Soc
14 Design of reconfigurable AHB arbiter
15 Efficient Codec Design for crosstalk avoidance codes based on numeral systems
16 Design and implementation of Picoblaze micro processor on FPGA.
17 Design of an AMBA AXI-APB bridge
18 A novel high speed design of a CAVLC encoder for H264 applications
19 A highly configurable MBIST architecture for very low area high fault coverage  BIST applications
20 An architecture for reducing the memory access latency in AMBA AHB based SOCs
21 Accumulator based 3-Weight Pattern Generation
22 Efficient compression schemes for AHB protocol signals for efficient tracing
23 A new approach to lut-based design and memory realization of FIR filter
24 Design of Hybrid Encoded Booth Multiplier with reduced switching activity Technique and Low power
25 Design of Non-linear variable cut-off High pass filter algorithm
26 Efficient implementation of 2D DCT and quantization architecture for JPEG compression
27 Design of TDES encryption  algorithm
28 I2c protocol interfaced EEPROM controller
29 Out of order Flash Controller
30 AXI Compliant DDR3 Controller
31 Design of an efficient Repairable RAM for high density memory
32 Concurrent BIST architecture based on square windows monitoring
33 A VLSI implementation of UART with BIST capability
34 Implementation of Self-motivated Arbitration Scheme for the multi layer AHB-BUS matrix
35 An efficient and high speed architecture for logarithm and anti logarithm
36 Multi mode low cost AES cryptography for security systems
37 Very Fast Pipelined RSA Architecture Based on Montgomery’s Algorithm
38 Power Optimization of Linear Feedback Shift Register (LFSR) for Low Power BIST
39 Low-Power CVNS-Based 64-Bit Adder for Media Signal Processing
40 ARM7 Compatible 32-Bit RISC Processor Design and Verification
41 MD5-based Error Detection
42 Bist approach for testing embedded memory blocks in System On Chips
43 Design of USB transceiver macro cell interface(UTMI) with USB 2.0
44 An efficient architecture for IEEE 754 floating point multiplication operations
45 Design and implementation of a field programmable CRC Circuit Architecture
46 Implementation of  a multi channel UART controller based on FIFO Technique and FPGA
47 AMBA based DMA controller
48 Optimized implementation of IEEE 802.3 transmitter
49 The design and implementation of AMBA interfaced high performance SDRAM controller for HDTV Soc
50 AMBA AHB bus protocol checker with efficient debugging mechanism

We will be providing the following details on CD:

  1. Abstract
  2. Datasheets
  3. Project report in PDF format and in doc (word) format
  4. Circuit diagram
  5. PCB layout
  6. Microcontroller program (software code)
  7. Sample power point presentation.
  8. Hex file of the microcontroller code
  9. Datasheets of all the components / ICs used in the project
  10. Photos & video file on entire project

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